The present invention relates to a complementary Bi-Mis (a bipolar semiconductor device combined with a metal insulator semiconductor device) gate circuit which includes a CMIS (complementary metal insulator semiconductor) circuits and a load driving inverter; the CMIS circuit comprising a PMIS (P type MIS) transistor and an NMIS (N type MIS) transistor and the load driving inverter comprising a pull-up transistor and a pull-down transistor are connected in series.
Each CMIS circuit is controlled so that a surge or short-circuit current (a first surge current) which flows through the CMIS circuit is reduced. The load driving inverter is also controlled so that a surge current (a second surge current) which flows through the driving inverter is removed. The first and second surge currents flow from a high potential source to a low potential source because respective transistors in the CMIS circuit and the driving inverter are simultaneously ON during a transient time in which an input signal applied to the gate circuit changes its level from low to high or from high to low.
Furthermore, the complementary Bi-MIS gate circuit is controlled so that a leakage current which flows in the gate circuit is stopped. The leakage current flows when the gate circuit is used as a 3-state circuit and is operating in a high impedance state.
The CMIS circuit is widely used as a logic semiconductor integrated circuit because the CMIS circuit has almost zero power consumption when in a steady state, a wide supply voltage range, a high input impedance and a low output impedance. A MOS (metal oxide semiconductor) transistor such as a PMOS (P type MOS) transistor or an NMOS (N type MOS) is a typical MIS transistor, so for convenience of explanation, a CMOS circuit and a Bi-MOS gate circuit will be discussed hereinafter.
The MOS transistor is a surface conductive type device having a lateral structure, and it is hard to drive very much current through a MOS transistor compared with a vertically structured semiconductor device like a bipolar transistor. Therefore, the complementary Bi-MOS gate circuit is usually composed of the CMOS circuits and a load driving inverter comprising a pull-up bipolar transistor and a pull-down bipolar transistor which are connected in series forming a totem pole type circuit. As a result, the high input impedance characteristic of the CMOS circuit and the low output impedance characteristic of the bipolar transistor are effectively utilized in the complementary Bi-MIS (Bi-MOS) gate circuit.
However, the complementary Bi-MOS gate circuit of the prior art has a problem in that first and second surge or short circuit currents flow in the gate circuit during a transient time when the transistors in the CMOS circuit and the load driving inverter are simultaneously ON. The surge currents produce noise which affects other circuits through a power source line, and increases the power dissipation and temperature of the complementary Bi-MOS gate circuit.